Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. As semiconductor device size become smaller and smaller, it becomes critical to develop enhanced semiconductor wafer inspection and review devices and procedures. Such inspection technologies include electron beam based inspection or review systems, such as, edge-of-wafer electron inspection or defect review tools.
The edge region of a wafer, such as 300 mm wafer, may represent approximately 10% of the total area used for device formation. However, the yield in the edge region may decrease by around 50% for various reasons. Interest in improved edge-of-wafer (EOW) inspection and review technologies to improve yield at the edge of wafers continues to grow. Due to the existence of fringe fields and the effects of such fringe fields, the EOW region of a given wafer is difficult to inspect and review. The existence of fringe fields may result in electron beam position error, defocus, astigmatism and/or blur.
Currently, defect location accuracy (DLA) and image quality (IQ) start degradation at approximately 5 mm from the wafer edge due to the existence of a fringe dipole field and fringe quadrupole field at the EOW. The fringe fields deflect electron beams and impact beam focus and stigmatism, especially for low landing energy (LE) beams. At the EOW, beam position, focus and stigmatism deviate from their calibrated values, so that defect review images become unusable at distances such as 1.9-5 mm towards the wafer edge. As such, it would be advantageous to provide a system and method that provides improved electron imaging at the edge regions of wafers so as to remedy the shortcomings identified above.